1. Field of the Invention
This invention relates to the field of ESD protection circuits for switching power converters.
2. Description of the Related Art
Common to all switching power converters is a switching element which, when driven to turn on, conducts a current to a “switching” node (SW). For several common configurations, a high-side switching element is connected between a voltage source (power supply) and the SW node, and a low-side switching element is connected between the SW node and circuit common or ground; during normal operation, the high- and low-side switching elements are alternately turned on and off as needed to charge and discharge an output inductor and capacitor and thereby provide a regulated output voltage.
All electronic circuits are susceptible to electro-static discharge (ESD) which can damage the circuit's components; this includes the switching elements of a switching power converter. This is particularly true when the low-side switching element is an n-channel MOSFET (NMOS FET), and as such, measures are often taken to protect the NMOS FET from being damaged by ESD. One way in which the NMOS FET can be protected from ESD is to design it with a larger-than-normal Drain-Contact-to-Gate-Spacing (DCGS). While this method works well for NMOS FETs having a channel width of a few thousands μm or less, it becomes impractical for switching power converters that utilize NMOS FETs having much greater channel widths—e.g., >10,000 μm. In this case, increasing the DCGS would require increasing the silicon die size to an economically uncompetitive level, and the FET's drain-source on-resistance (Rdson) would become unacceptably high.
With a large NMOS FET, “active” ESD protection—i.e., circuitry which detects ESD events and triggers an appropriate protective response—is often employed. One common method is to use an active ESD protection circuit to force the NMOS FET to turn on, so that an ESD discharge path is provided between the SW node and ground by the NMOS FET's channel. However, making such a circuit stable and reliable can be a daunting task, for several reasons.
Such circuitry is typically connected directly to the SW node, to enable an ESD event to be detected; this arrangement is referred to as ‘direct sensing’. When a very large NMOS FET is forced to turn on by the active ESD circuit, the SW node will be pulled to ground potential nearly instantaneously, since the NMOS FET's Rdson is usually on the order of milliohms. This results in the ESD circuit losing its power, which causes the NMOS FET to turn off. However, if the ESD event has not finished when this occurs, the remainder of the ESD charge will force the voltage on the SW node to shoot up again, which triggers another cycle as described above. Also, if the active ESD circuit does not respond quickly enough, or does not retrigger following a previous trigger event for some reason, the NMOS FET can still be damaged. This results in unreliable ESD protection or unstable oscillatory behavior.
A direct sensing arrangement can also cause the ESD protection circuit to falsely trigger during normal operation. This can occur because very fast and very large switching spikes—comparable to those associated with ESD events—are constantly present on the SW node.
As noted above, a common protective method is to force the NMOS FET to turn on. This is typically achieved by having the ESD protection circuit generate an active-high ‘trigger signal’ when an ESD event is detected, which is directly applied to the gate of the NMOS FET; this arrangement is referred to as ‘direct coupling’. When so arranged, the ESD trigger signal and the control signal which operates the NMOS FET under normal operating conditions will physically share the same node. However, during an ESD event, the state of the normal operations signal is unknown, and it is possible that the two signals will conflict and render the ESD protection unreliable.
Another problem can occur if the low-side switching element is turned on to provide a conductive path between the SW node and ground during an ESD event, without regard to the status of the high-side switching element. If the high-side switching element happens to be on while the low-side switching element is on, a ‘shoot-through’ condition occurs which can cause severe damage to the switching elements of the power converter, especially when false triggering occurs during normal operations.